1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to methods for determining a geometrical configuration of an interconnect structure of a test structure.
2. Background Art
It is difficult to obtain geometrical configurations or dimensions of typical high-performance digital interconnect structures. Currently, there is no way to determine the geometrical configuration of an interconnect structure of a test structure other than by cross-sectioning a wafer containing the test structure, which destroys the wafer, and performing some sort of measurement analysis, e.g., using a scanning electron microscope (SEM). This process is time consuming and is never comprehensive because it cannot be applied to all interconnect structures on a wafer.